A voltage regulator is a circuit designed to automatically maintain a constant voltage level. A DC voltage regulator may be used to stabilize a DC voltage used by a load, such as a processor or an analog circuit that is sensitive to fluctuation in supply voltage.
In general, performance of a voltage regulator may be qualified by its ability to perform two functions, namely providing a known accurate output regulated voltage, and ensuring that the regulated voltage remains substantially impervious to changes in the supply voltage.
A simple voltage regulator may comprise a series combination of a resistor and a diode. The voltage across the diode changes only slightly in response to changes in the input voltage since the diode's voltage-current response is substantially logarithmic. Such regulators may be suitable if precision in the regulated voltage is not a significant concern. In other words, while the second function of a regulator may be satisfied, the first function may not be.
FIG. 1 shows an example of a more complex voltage regulator circuit. The regulator, shown generally at 10, is provided with a supply voltage VDD 1, that has both a DC component 2 and a noise component 3. In some cases, the supply voltage VDD 1 may be less than 1 VDC, making it suitable for CMOS integrated circuit (IC) applications. The regulator 10 attempts to generate an output regulated voltage VReg 4. The regulated voltage VReg 4 is less than the supply voltage VDD 1. The regulated voltage VReg 4 may be tuned by selection of a known, desired reference voltage VRef 5, which may in some cases be set to a fraction between 0.5 and 0.75 of the supply voltage VDD 1, in the presence of a load circuit 6. The load 6 is coupled at respective ends between the regulated voltage VReg 4 and ground.
In some cases, the load 6 may be a high-speed circuit, such as a voltage-controlled oscillator (VCO). A typical VCO circuit that may serve as the load 6, is shown in FIG. 1A. As may be seen, the VCO circuit may incorporate a plurality of MOS transistors. A change in the voltage supplied to a load 6, may cause the parameters of MOS transistors in the load 6, such as threshold voltage, gate capacitance and transconductance, to vary.
Where the load 6 is a high-speed circuit, the performance of the voltage regulator may be further qualified by a third function, namely that the regulated voltage VReg 4 and reference voltage VRef 5 exhibit low flicker noise. Flicker noise is a resistance fluctuation related to a direct current that is transformed to a voltage or current fluctuation through the operation of Ohm's law. Flicker noise manifests itself as a type of electronic noise having a power density spectrum as a function of frequency f, which may be modelled as 1/f. While flicker noise typically shows up as a low-frequency phenomenon, in frequency conversion circuits, such as an oscillator, such low-frequency noise may be heterodyned up to frequencies close to the carrier frequency, which may cause oscillator phase noise. Flicker noise in a supply voltage for a VCO may introduce noise in the oscillating signal that may introduce data reception and/or transmission errors, especially the VCO clock is used in a wireless and/or wireline data transmitter and/or receiver.
The VCO may be used to generate clocks in various electronic systems including high-speed serializer-deserializer (SerDes) applications. Such systems employ high clock purity signals. Such signals may be described in terms of deterministic and random jitter or phase noise.
Where the VCO is employed for phase locked loop (PLL) applications, variation in the supply voltage for the VCO may shift the VCO frequency beyond a range for which the PLL can provide compensation, resulting in the loss of phase lock.
The regulator 10 may comprise a transistor 7, a resistor 8, a decoupling capacitor 9 and a control circuit 11. The transistor 7 and resistor 8 comprise a voltage-controlled current source that acts as a pass-gate for driving the regulated voltage VReg 4. The capacitor 9 shunts any high frequency fluctuation of the regulated voltage VReg 4 to ground.
The transistor 7 may be an enhanced PMOS transistor that has a source 12, bulk 13, drain 14 and gate 15. The bulk 13 and source 12 are coupled together and to a first end of the resistor 7 and tied to the supply voltage VDD 1. The drain 14 is coupled to the second end of the resistor 8 and to a first end of the capacitor 9 and provides the regulated output voltage VReg 4 signal. The gate 15 is coupled to an output of the control circuit 11. The transistor 7 draws current from the supply voltage 1 when enabled by the output 17 of the DAC. The regulated voltage VReg 4 is less than the supply voltage VDD 1 by a DC drop between the source 12 and drain 14 of the transistor 7.
The first end of the resistor 8 is coupled to the source 12 and bulk 13 of the transistor 7 and tied to the supply voltage 1. The second end of the resistor 8 is coupled to the first end of the capacitor 9 and to the drain 14 of the transistor 7 and provides the regulated voltage VReg 4 signal. The resistor 8 may, in some cases, be used in conjunction with the transistor 7 to provide a small quiescent current to the load 6. The amount of current flowing through the load 6 may be adjusted by selective adjustment of the control circuit 11
The first end of the capacitor 9 is coupled to the second end of the resistor 8 and to the drain 14 of the transistor 7 and provides the regulated voltage VReg 4 signal. The second end of the capacitor 9 is grounded. The capacitor 9 decouples the regulated voltage, reducing its high frequency noise. In order to reduce log flicker (1/f) noise, it may be desirable to make the capacitor 9 extremely large. However, doing so is usually contra-indicated in “on-die” silicon implementations.
The control circuit 11 provides an output signal for controlling the voltage-controlled current source. The control circuit 11 has a control input 16, and output 17 and two switches 18, 19 that respectively couple the reference voltage VRef 5 and the supply voltage VDD 1 to the output 17. The control input 16 opens one of the switches 18, 19 and simultaneously closes the other switch 19, 18 so that the output 17 reflects a voltage level that may be set to one of the supply voltage VDD 1 and the reference voltage VRef 5, in accordance with the control input 16, to drive the voltage-controlled current source. The control input 16 is a static value that varies in time only to reflect temperature variations that are, by way of example, at least six orders of magnitude slower than changes in the current through the load 6. The control input 16 may reflect the temperature and SMOS process corner. The process corner is a design-of-experiments (DoE) technique used in semiconductor manufacturing to vary fabrication parameters used in applying an integrated circuit (IC) design to a semiconductor wafer.
The regulator 10 uses PMOS gates and resistors instantiated between the supply voltage VDD 1 and the regulated voltage VReg 4. When appropriately sized, these isolate the regulator 10 from the supply voltage VDD 1. The regulator 10 exhibits low flicker and thermal noise on the regulated voltage VReg 4, but suffers from poor load and line regulation precision and poor supply noise rejection especially at low supply voltages VDD 1, when the voltage drop on the resistor 8 or the PMOS gate 15 is below 0.4V. Additionally, the quality of the load and line regulation, supply noise rejection, temperature coefficient, dropout voltage and initial accuracy of the regulator 10 are highly dependent upon the process corner (that is, variation of the silicon parameters of the IC from lot to lot or within a given lot of samples due to manufacturing imperfections) and variations in the supply voltage VDD 1 and/or temperature. Such variations are known as Process, Voltage, Temperature (PVT) variations.
FIG. 2 shows an operational amplifier (Op-Amp) based voltage regulator configuration. The regulator, shown generally at 20, comprises the voltage-controlled current source comprising the transistor 7 and capacitor 9 of FIG. 1, but with an Op-Amp 21 in place of the static control circuit 11. The transistor 7 is configured in a manner similar to that of FIG. 1, with the exception that the gate 15 is coupled to an output 24 of the Op-Amp 21 rather than the control circuit 11.
The Op-Amp 21 has two inputs 22, 23 and an output 24. The first input 22 is coupled to the reference voltage VRef 5. The second input 23 is coupled to the regulated voltage VReg 4 or, in some cases, to a scaled version (not shown). The output 24 is coupled to the gate 15 of the transistor 7 and provides the control signal that drives the voltage-controlled current source. Thus, the combination of the Op-Amp 21 and transistor 7 provides a feedback loop that causes the regulated voltage VReg 4 to approach, track and lock to the reference voltage VRef 5 with high precision, defined by a frequency-dependent loop gain, which in some cases may be more than 10, of such system. The loop gain is defined by the bandwidth of the Op-Amp 21 and dependent upon the gain of the Op-Amp 21 and the transconductance of the transistor 7, as well as a scaling factor applied on the regulated voltage VReg 4. If the frequency of the noise component 3 of the supply voltage VDD 1 is less than unit gain, the regulator 20 exhibits good line and load regulation over PVT, as may be seen by a plot of the loop gain as a function of frequency (not shown).
The regulator 20 exhibits good regulation precision and good supply noise rejection at low supply voltages VDD 1. Additionally, the performance is less dependent upon ambient PVT conditions. Unlike the regulator 10 of FIG. 1, the (1/f) flicker noise of the regulator 20 will not be reduced, even by making the capacitor 9 very large. Accordingly, the regulator 20 does exhibit high flicker and thermal noise on the regulated voltage VReg 4, due to inherent high flicker noise of the Op-Amp 21 and amplification of the flicker and thermal noise within the loop through the loop gain.
A further voltage regulator circuit using a strong-arm latch comparator to supplement data-driven open-loop current is discussed in Kavlani, K., et al “A 6.4 GB/s Near-Ground Single-ended Transceiver for Dual-Rank DIMM Memory Interface Systems” IEEE International Solid-State Circuits Conference, 20 Feb., 2013, pp, 306-308, and is generally shown in FIG. 3. The circuit, shown generally at 30, comprises a regulator circuit 31, an open loop current source circuit 25 and decoupling capacitor 9. Capacitor 9 may be on the order of 76 pF.
The regulator circuit 31 comprises a comparator 32 and a first transistor 37. The comparator 32 has two inputs 33, 34, an output 35 and a clock input 36. The first input 33 is coupled to the reference voltage VRef 5, which may be nominally set to a fraction of 0.5 of the supply voltage VDD 1 and the second input 34 is coupled to the regulated voltage VReg 4. The comparator output 35 is coupled to the gate of the first transistor 37. The clock input 36 provides a clock signal, which may be on the order of 3.2 GHz, to clock the comparator 32. The clock signal is comparable to the transmitter clock, which is nominally 0.5 of the maximum data rate. The comparator 32 compares the reference voltage VRef 5 and the regulated voltage VReg 4 presented at its respective inputs 33, 34 and generates an error signal for each clock cycle that it presents, at the comparator output 35, to the gate of the first transistor 37. Thus, the comparator 32 provides a digital error signal at the clock rate provided at the clock input 36 to drive the first transistor 37.
The first transistor 37 may be a PMOS enhanced MOSFET with bulk (not shown) connected to the source or a substrate of the first transistor 37, whose gate is coupled to the comparator output 35. The source of the first transistor 37 is coupled to the source of a second transistor 38 in the open loop current source circuit 25 and tied to the supply voltage VDD 1. The drain of the first transistor 37 is coupled to the drain of second transistor 38 in the open loop current source circuit 25 and to the first end of decoupling capacitor 9 and provides the regulated voltage VReg 4. The first transistor 37 draws current (IClosed) from the supply voltage VDD 1 when enabled by the comparator output 35 to supply the regulated voltage VReg 4.
The regulator circuit 31 acts as a closed-loop (the current supplied at 35 to the regulated voltage VReg 4 and the load 6 tends to track the regulated voltage VReg 4) current source that provides current draw for the regulated voltage VReg 4 when the open-loop (the current supplied at 38 to the regulated voltage VReg 4 and the load 6 tends to depend upon the data input 27 only) current source circuit 25 is not. In effect, the regulator circuit 31 incorporates a 1-bit analog-to-digital converter (ADC) with no corresponding digital-to-analog converter (DAC) as a backup when the data 28 is a “0”, to keep the regulated voltage VReg 4 from collapsing to ground in the event of a protracted sequence of “0” s in the data stream 28.
The open-loop current source circuit 25 comprises an AND gate 26 and a second transistor 38. The AND gate 26 has first and second inputs 27, 28 and an output 29. The first input 27 is coupled to a data enable signal. The second input 28 is coupled to a data stream. The output 29 of the AND gate 26 is a “1” when the data presented at the second input 28 is a “1” and the data enable signal at the first input 27 is also a “1” (enabled). Thus, the open-loop circuit 25 only draws current (IClosed) from the supply voltage VDD 1 when the signal at the gate 29 is a “0” to supply the regulated voltage VReg 4.
The second transistor 38 may be a PMOS enhanced MOSFET, whose gate is coupled to the output 29 of the AND gate 26. The source of the second transistor 38 is coupled to the source of the first transistor 37 in the regulator circuit 31 and tied to the supply voltage VDD 1. The drain of the second transistor 38 is coupled to the drain of the first transistor 37 in the regulator circuit 31 and to the first end of decoupling capacitor 9 and provides the regulated voltage VReg 4. The second transistor 38 draws current (IOpen) from the supply voltage VDD 1 when the data presented at the second input 28 of the AND gate 26 is a “0” and the data enable signal at the first input 27 is also a “1” (enabled) to supply the regulated voltage VReg 4.
The open-loop circuit 25 serves an auxiliary function to source additional current when the data presented at the second input 28 of the AND gate 26 is a long stream of “0” s or “1” s during which the transistor 38 acts as a fully closed or fully open switch. In a nominal case, the open-loop circuit 25 may source on the order of 90% of the current to supply the regulated voltage VReg 4. However, the ripple generated by the circuit 30 may be several percent of the reference voltage VRef 5, without even accounting for the noise 3 in the supply voltage, rendering it unsuitable for a high-speed load 6, such as a VCO.